Calculate a decoupling capacitor value from target impedance and frequency, or from a current step and allowed droop, then check ESR and ESL.
Decoupling Capacitor Formulas
The widget sizes ideal capacitance from target impedance or a constant current deficit, or estimates a capacitor bank’s series-RLC impedance. Optional capacitance loss applies in all three modes. The two sizing modes round nominal capacitance upward to an E12 value; that is a mathematical starting point, not validation of a selected part.
Target impedance mode
- C = minimum capacitance, in farads
- f = noise or switching frequency, in hertz
- Z = target PDN impedance, in ohms
This treats the capacitor as an ideal element where |ZC| = 1/(2Ï€fC). Real capacitors hit a series resonance and become inductive above it, so this result is only valid up to the part’s SRF. If you do not have a target impedance, use Z = ΔVallowed / Itransient.
Current-step droop mode
Effective C = current deficit × response interval / allowed capacitive droop. For a varying deficit, integrate current over time. Nominal C = effective C / (1 − loss/100). ESR and ESL voltage changes require separate allowance.
Real capacitor bank mode
For N identical independent parts, Cbank = N × Cnominal × (1 − loss/100), ESRbank = ESRpart/N and ESLbank = ESLpart/N. SRF = 1/(2π√(ESLbank × Cbank)) for positive ESL; |Z| = √[ESRbank² + (2πfESLbank − 1/(2πfCbank))²]. Shared mounting inductance is excluded.
Supplementary sinusoidal ripple formula
- C = minimum capacitance, in farads
- I_ripple = peak-to-peak ripple current, in amps
- f = ripple frequency, in hertz
- V_ripple = allowed peak-to-peak ripple voltage, in volts
This assumes a sinusoidal ripple and ignores ESR. Evaluate capacitive ripple and VESR = Iripple × ESR using a consistent waveform convention, along with inductive spikes and the regulator stability requirements. Their relative importance depends on the part and circuit.
Supplementary digital charge estimate
- C_decouple = minimum decoupling capacitance, in farads
- N = number of simultaneously switching outputs
- C_load = load capacitance per output, in farads
- dV_signal = signal voltage swing, in volts
- dV_supply = maximum allowed supply dip, in volts
This comes from charge conservation: the charge pulled to drive the loads (N × Cload × ΔVsignal) must come from the decoupling cap without dropping its voltage by more than ΔVsupply. Rise time is optional and only used to estimate peak current as Ipeak = Q/tr; it does not change the capacitance result.
Reference Tables
These are illustrative starting points, not product recommendations. Check the device requirements and actual part impedance, bias, temperature, ratings and mounting model.
| Application | Typical value | Dielectric / type |
|---|---|---|
| Per-pin logic decoupling | 100 nF | X7R MLCC, 0402/0603 |
| High-speed FPGA / SoC core | 10 nF + 100 nF + 1 µF | X5R/X7R MLCC stack |
| Bulk rail decoupling | 10 to 100 µF | MLCC, polymer, or tantalum |
| Switching regulator output | 22 to 220 µF | Polymer or low-ESR electrolytic |
| RF / GHz coupling | 1 to 100 pF | C0G/NP0 MLCC |
| Frequency range | Possible type to evaluate | Why |
|---|---|---|
| DC to ~10 kHz | Bulk electrolytic or polymer (10 to 1000 µF) | High capacitance keeps low-frequency impedance down |
| 10 kHz to 1 MHz | Tantalum or large MLCC (1 to 10 µF) | Bridges bulk and ceramic regions |
| 1 MHz to 100 MHz | X7R MLCC (10 nF to 1 µF) | Verify the actual part’s SRF and impedance curve |
| 100 MHz to several GHz | Small C0G MLCC (1 to 100 pF) in 0201/0402 | Low ESL dominates above 100 MHz |
Worked Examples
Example 1: Target impedance for a 100 MHz noise source
A digital rail allows a 50 mV dip with 1 A of transient current. Target impedance is 50 mV / 1 A = 0.05 Ω. At 100 MHz:
C = 1 / (2π × 100 × 106 × 0.05) ≈ 31.8 nF
The ideal E12 round-up is 33 nF before any capacitance loss. A real part is not validated at 100 MHz by that number; check ESR, ESL, bias and mounting impedance, and minimize the connection loop.
Example 2: Switching outputs on a microcontroller
Eight outputs switch into 30 pF loads with a 3.3 V swing. You allow a 100 mV supply dip.
C = 8 × 30 pF × 3.3 V / 0.1 V = 7.92 nF
A nominal 10 nF part exceeds this ideal charge estimate before derating. High-frequency performance depends on the actual ESR, ESL and layout; larger capacitance alone does not guarantee better high-frequency decoupling.
FAQ
Why does my real PDN impedance not match the calculated value? The formula ignores ESR, ESL, mounting inductance, and plane spreading inductance. Above the capacitor’s self-resonant frequency, ESL dominates and the impedance rises again.
Should I use one big cap or several small ones? Several smaller capacitors in parallel lower ESL and give a wider low-impedance band. Mixing values can create anti-resonance peaks; using many of the same value usually gives a flatter response.
How much does DC bias matter? Capacitance loss depends on dielectric, package, voltage rating and the exact part. Use the manufacturer’s bias and temperature curves and tolerance data rather than assuming a universal percentage.
Where do I place the capacitor? As close to the supply pin as the layout allows, with short, wide traces or vias to the power and ground planes. Loop inductance from the cap to the pin sets the high-frequency limit, not the capacitance value.
