Enter the peak-to-peak ripple current, frequency of the ripple, and peak-to-peak ripple voltage into the calculator to determine the capacitance of the decoupling capacitor. This calculator can also evaluate any of the variables given the others are known.
Decoupling Capacitor Formulas
The calculator uses a different formula for each mode. All three return a minimum capacitance. Round up to the next available standard value and add margin for ESR, ESL, DC bias derating, and temperature.
Target impedance mode
C = 1 / (2 * pi * f * Z)
- C = minimum capacitance, in farads
- f = noise or switching frequency, in hertz
- Z = target PDN impedance, in ohms
This treats the capacitor as an ideal element where |ZC| = 1/(2πfC). Real capacitors hit a series resonance and become inductive above it, so this result is only valid up to the part’s SRF. If you do not have a target impedance, use Z = ΔVallowed / Itransient.
Ripple current mode
C = I_ripple / (2 * pi * f * V_ripple)
- C = minimum capacitance, in farads
- I_ripple = peak-to-peak ripple current, in amps
- f = ripple frequency, in hertz
- V_ripple = allowed peak-to-peak ripple voltage, in volts
This assumes a sinusoidal ripple and ignores ESR. For a switching regulator output, ESR usually dominates ripple, so check VESR = Iripple × ESR separately and use the larger of the two values.
Digital switching mode
C_decouple = N * C_load * dV_signal / dV_supply
- C_decouple = minimum decoupling capacitance, in farads
- N = number of simultaneously switching outputs
- C_load = load capacitance per output, in farads
- dV_signal = signal voltage swing, in volts
- dV_supply = maximum allowed supply dip, in volts
This comes from charge conservation: the charge pulled to drive the loads (N × Cload × ΔVsignal) must come from the decoupling cap without dropping its voltage by more than ΔVsupply. Rise time is optional and only used to estimate peak current as Ipeak = Q/tr; it does not change the capacitance result.
Reference Tables
Use these to sanity-check the result and pick a real part.
| Application | Typical value | Dielectric / type |
|---|---|---|
| Per-pin logic decoupling | 100 nF | X7R MLCC, 0402/0603 |
| High-speed FPGA / SoC core | 10 nF + 100 nF + 1 µF | X5R/X7R MLCC stack |
| Bulk rail decoupling | 10 to 100 µF | MLCC, polymer, or tantalum |
| Switching regulator output | 22 to 220 µF | Polymer or low-ESR electrolytic |
| RF / GHz coupling | 1 to 100 pF | C0G/NP0 MLCC |
| Frequency range | Capacitor that handles it best | Why |
|---|---|---|
| DC to ~10 kHz | Bulk electrolytic or polymer (10 to 1000 µF) | High capacitance keeps low-frequency impedance down |
| 10 kHz to 1 MHz | Tantalum or large MLCC (1 to 10 µF) | Bridges bulk and ceramic regions |
| 1 MHz to 100 MHz | X7R MLCC (10 nF to 1 µF) | SRF and low ESL fall in this band |
| 100 MHz to several GHz | Small C0G MLCC (1 to 100 pF) in 0201/0402 | Low ESL dominates above 100 MHz |
Worked Examples
Example 1: Target impedance for a 100 MHz noise source
A digital rail allows 50 mV dip with 1 A of transient current. Target impedance is 50 mV / 1 A = 0.05 Ω. At 100 MHz:
C = 1 / (2π × 100 × 106 × 0.05) ≈ 31.8 nF
Pick a 33 nF or 100 nF X7R MLCC. Place it within a few millimeters of the supply pin.
Example 2: Switching outputs on a microcontroller
Eight outputs switch into 30 pF loads with a 3.3 V swing. You allow 100 mV supply dip.
C = 8 × 30 pF × 3.3 V / 0.1 V = 7.92 nF
A 10 nF capacitor meets the math, but a 100 nF part is the standard choice because it absorbs higher-frequency content as well.
FAQ
Why does my real PDN impedance not match the calculated value? The formula ignores ESR, ESL, mounting inductance, and plane spreading inductance. Above the capacitor’s self-resonant frequency, ESL dominates and the impedance rises again.
Should I use one big cap or several small ones? Several smaller capacitors in parallel lower ESL and give a wider low-impedance band. Mixing values can create anti-resonance peaks; using many of the same value usually gives a flatter response.
How much does DC bias matter? A lot. A 10 µF X5R 0402 rated for 6.3 V can lose 60% to 80% of its capacitance at 3.3 V. Always check the manufacturer’s bias curve and oversize accordingly.
Where do I place the capacitor? As close to the supply pin as the layout allows, with short, wide traces or vias to the power and ground planes. Loop inductance from the cap to the pin sets the high-frequency limit, not the capacitance value.
